The adoption of high-speed serial data interfaces and the move to smaller semiconductor manufacturing geometries is necessary for cost, integration, and performance factors, but this smaller geometry is also more prone to ESD damage at lower voltage and current levels. Additionally, low-capacitance ESD devices required on high-speed data lines tend to have higher dynamic resistance as their capacitance decreases, making them less capable of protecting sensitive ICs in the system.
With traditional ESD protection, an inverse relationship exists between robust ESD protection and good signal integrity. Some ASICs have no acceptable traditional ESD device that can provide required ESD protection levels combined with acceptable signal integrity.
Datasheet specifications
System designers often compare ESD protection devices using device datasheet ESD-level ratings. These ratings only guarantee what the ESD device, not what the system, will survive.
A device rated for 8 kV can fail a system-level test at 2 kV or lower. In other cases, a device rated for 15 kV may not protect a system as well as an 8-kV rated device. This primary parameter that most system designers use to compare ESD devices gives no indication of the actual system-level performance.
System ICs can be damaged by excessive voltage, excessive current, or both. Many system designers are aware that excessive voltage can damage an IC, but are unaware that high current levels are often the real cause of ESD damage.
Fig. 1. In traditional ESD protection architectures, an inverse relationship exists between protection and signal integrity.
ESD protection devices function by shunting most of the current to ground and 'clamping' the voltage seen at the ASIC to a lower value than the strike voltage. Ideally, the way to compare ESD devices is to examine their clamping voltage and residual current (the current that does not get shunted through the ESD device). However, this is easier said than done.
Clamping voltage
The clamping voltage quoted in most ESD protection datasheets can be misleading. Current industry practice is to publish clamping voltages based on a pulse with an 8-µs rise time and duration of 20 µs.
Most datasheets document clamping voltage using a 1-A pulse and sometimes a higher-current pulse as well. This pulse is used because it is repeatable and easy to measure. Unfortunately, this pulse is not equivalent to an ESD pulse, which has a 1-ns rise time and a duration of 60 ns. Also, the clamping voltage during a level 4 IEC 61000-4-2 strike with a peak current of 30 A is much different than seen during a 1-A pulse.
Using the standard 1-A pulse, most semiconductor ESD protection diodes are rated to clamp between 8 and 15 V. Confronted with an 8-kV IEC 61000-4-2 strike, these diodes typically show peak clamping voltages of 50 to 100 V, depending on other diode characteristics such as dynamic resistance.
Some ESD vendors also include ESD pulse waveforms, but these can also be misleading. For example, vendors typically use attenuators to keep from damaging their test equipment. When shown on a waveform plot, the clamping voltage in the datasheet often does not show the impact of the attenuator, misstating the clamping voltage by a factor of 5 to 10 times.
Although it is not possible to compare ESD performance solely using the clamping voltages shown in most datasheets, there are ways to compare relative performance by reading the datasheet carefully.
